Posts by Category

EDA

UVM Learning Path

This article provides a review of UVM learning resources, complete example projects, and useful tools to expedite the learning process.

Verilog/SystemVerilog Setup in Vim

This post guides you through setting up Verilog/SystemVerilog in Vim, covering ctags generation and linting. While vim-ale is often seen as an optimal soluti...

Euclide - Part0

本文介绍Synopsys的前端设计IDE Euclide。

Back to top ↑

UVM

UVM Learning Path

This article provides a review of UVM learning resources, complete example projects, and useful tools to expedite the learning process.

Verilog/SystemVerilog Setup in Vim

This post guides you through setting up Verilog/SystemVerilog in Vim, covering ctags generation and linting. While vim-ale is often seen as an optimal soluti...

Back to top ↑

Front-End

Coverage 用法总结

本文介绍Coverage的概念以及使用Synopsys工具对其进行分析的方法。

DC High Fanout Nets

本文介绍 DC 综合阶段 High-Fanout Nets 可能遇到的相关问题

Euclide - Part0

本文介绍Synopsys的前端设计IDE Euclide。

Back to top ↑

Vim

Vim UVM Snippets

This article outlines the process of adding UVM snippets to the vim-snippet GitHub repository.

vim-galore enhanced

The repository vim-galore is an excellent resource for Vim learners, focusing on fundamental Vim capabilities. However, to further augment Vim’s functionalit...

Back to top ↑

SSD

SSD Controller Verification

This article provides insights into considerations for SSD Controller Functional Verification.

Back to top ↑

jekyll

Back to top ↑

update

Back to top ↑

RISC-V

Back to top ↑

Debug

Back to top ↑

Opt

Back to top ↑

Back-End

ICC Custom Floorplan

本文介绍 ICC 进行特定形状的 Floorplan 设计以及PIN脚摆放的方法。

Back to top ↑

ssd

NVMe Introduction

Introduction to Non-Volatile Memory Express (NVMe) Interface for Beginners.

Back to top ↑